FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both − + multipliers using same hardware structure with only one control signal. A novel proposed achieve superior performance, low power, fast operation, high area efficiency, area-delay product (ADP) power-delay (PDP) compared similar modified Booth-encoding methods. In addition, by integrating separate functions of into single multiplier, method save up to 52.59% (n = 16) area, 5.45% 32) delay time, 49.05% dynamic 50.92% ADP, 50.02% PDP original circuits merged together. Furthermore, operation ranges multiplicand are {0, 2n 1} 2n}, respectively, which wider than for other reported structures. power consumption, time simulated verified Verilog HDL Xilinx FPGA (Field Programmable Gate Array) Vivado tools. Artix-7 XC7A35T-CSG324-1 chipset adopted work.